ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE
Author affiliations
DOI:
https://doi.org/10.15625/1813-9663/37/2/15917Keywords:
NB-LDPC, Basic-set, Trellis min-max, VLSI designAbstract
Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.
Metrics
References
H.C. Davey, D.J. MacKay, Low density parity check codes over GF (q), in: Information Theory Workshop, 1998, IEEE, 1998, pp. 70-71.
R. Peng, R.R. Chen, WLC45-2: Application of Nonbinary LDPC Codes for Communication over Fading Channels Using Higher Order Modulations, in: IEEE Globecom 2006, 2006, pp. 1-5.
M. Arabaci, I.B. Djordjevic, L. Xu, T. Wang, Nonbinary LDPC-Coded Modulation for High-Speed Optical Fiber Communication Without Bandwidth Expansion, IEEE Photonics Journal, 4 (2012) 728-734.
Z. Cui, Z. Wang, X. Huang, Multilevel error correction scheme for MLC flash memory, in: 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, pp. 201-204.
D. Declercq, M. Fossorier, Decoding algorithms for nonbinary LDPC codes over GF $(q) $, IEEE Transactions on Communications, 55 (2007) 633-643.
V. Savin, Min-Max decoding for non binary LDPC codes, in: Information Theory, 2008. ISIT 2008. IEEE International Symposium on, IEEE, 2008, pp. 960-964.
F. Cai, X. Zhang, Relaxed min-max decoder architectures for nonbinary low-density parity-check codes, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 21 (2013) 2010-2023.
J.O. Lacruz, F. García-Herrero, D. Declercq, J. Valls, Simplified Trellis Min–Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 23 (2015) 1783-1792.
J.O. Lacruz, F. Garcia-Herrero, J. Valls, D. Declercq, One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes, Circuits and Systems I: Regular Papers, IEEE Transactions on, 62 (2015) 177-184.
H.P. Thi, H. Lee, Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (2017).
J.O. Lacruz, F. García-Herrero, M.J. Canet, J. Valls, Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24 (2016) 2643-2653.
H.P. Thi, H. Lee, Basic-Set Trellis Min–Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26 (2018) 496-507.
J.O. Lacruz, F. Garcia-Herrero, J. Valls, Reduction of complexity for nonbinary LDPC decoders with compressed messages, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 23 (2015) 2676-2679.
J. Lacruz, F. Garcia-Herrero, M. Canet, J. Valls, A. Perez-Pascual, A 630 Mbps non-binary LDPC decoder for FPGA, in: Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, IEEE, 2015, pp. 1989-1992.
J.O. Lacruz, F. Garcia-Herrero, M.J. Canet, J. Valls, High-performance NB-LDPC decoder with reduction of message exchange, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24 (2016) 1950-1961.
H.P. Thi, C.D. The, N.P. Xuan, H.D. Tuan, H. Lee, Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder, in: 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), IEEE, 2019, pp. 213-216.
B. Zhou, J. Kang, S. Song, S. Lin, K. Abdel-Ghaffar, M. Xu, Construction of non-binary quasi-cyclic LDPC codes by arrays and array dispersions-[transactions papers], Communications, IEEE Transactions on, 57 (2009) 1652-1662.
J. Lin, J. Sha, Z. Wang, L. Li, Efficient decoder design for nonbinary quasicyclic LDPC codes, Circuits and Systems I: Regular Papers, IEEE Transactions on, 57 (2010) 1071-1082.
C.-L. Wey, M.-D. Shieh, S.-Y. Lin, Algorithms of finding the first two minimum values and their hardware implementation, IEEE Transactions on Circuits and Systems I: Regular Papers, 55 (2008) 3430-3437.
Downloads
Published
How to Cite
Issue
Section
License
1. We hereby assign copyright of our article (the Work) in all forms of media, whether now known or hereafter developed, to the Journal of Computer Science and Cybernetics. We understand that the Journal of Computer Science and Cybernetics will act on my/our behalf to publish, reproduce, distribute and transmit the Work.2. This assignment of copyright to the Journal of Computer Science and Cybernetics is done so on the understanding that permission from the Journal of Computer Science and Cybernetics is not required for me/us to reproduce, republish or distribute copies of the Work in whole or in part. We will ensure that all such copies carry a notice of copyright ownership and reference to the original journal publication.
3. We warrant that the Work is our results and has not been published before in its current or a substantially similar form and is not under consideration for another publication, does not contain any unlawful statements and does not infringe any existing copyright.
4. We also warrant that We have obtained the necessary permission from the copyright holder/s to reproduce in the article any materials including tables, diagrams or photographs not owned by me/us.