Analytical threshold voltage and drain-induced barrier lowering models of elliptic junctionless Gate-All-Around FET
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https://doi.org/10.15625/2525-2518/20573Keywords:
Elliptic, Gate-All-Around, Threshold voltage, DIBL, EccentricityAbstract
The analytical models have been presented to determine the threshold voltage and Drain-Induced Barrier Lowering (DIBL) of an elliptic junctionless Gate-All-Around (GAA) FET. Because it is difficult to fabricate a GAA FET with an accurate circular cross-section, an analysis of an elliptic GAA FET is required. The values obtained using the proposed analytical threshold voltage and DIBL models were confirmed to be in good agreement, compared to other papers that had already been verified. Using this analytical threshold voltage and DIBL models, the threshold voltage and DIBL were analyzed according to the eccentricity of the elliptic cross-section structure. As a result, it was found that the absolute value of the minimum central potential increases as eccentricity increases, thereby increasing the threshold voltage. Additionally, the absolute value of the minimum central potential decreases as the drain voltage increases, thereby decreasing the threshold voltage, and this decreasing rate, i.e. DIBL, reduces as eccentricity increases. Therefore, threshold voltage and DIBL showed a mutual trade-off relationship for eccentricity. The threshold voltage and DIBL showed little change when the eccentricity was less than about 0.75. However, the threshold voltage and DIBL showed a large change along with a decrease in the effective channel radius when it was more than 0.75.
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