JUNG, Hakkee. Analytical threshold voltage and drain-induced barrier lowering models of elliptic junctionless Gate-All-Around FET . <b>Vietnam Journal of Science and Technology</b>, Hanoi, VN, v. 63, n. 6, p. 1192–1204, 2025. DOI: 10.15625/2525-2518/20573. Disponível em: https://vjs.ac.vn/jst/article/view/20573. Acesso em: 9 jan. 2026.