@article{NGUYEN_LE_BUI_HUYNH_PHAM_2018, title={A flexible high-bandwidth low-latency multi-port memory controller}, volume={56}, url={https://vjs.ac.vn/index.php/jst/article/view/11103}, DOI={10.15625/2525-2518/56/3/11103}, abstractNote={<span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">Multi-port memory controllers (MPMCs) have become increasingly important in many <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">modern applications due to the tremendous growth in bandwidth requirement. Many approaches <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">so far have focused on improving either the memory access latency or the bandwidth utilization <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">for specific applications. Moreover, the application systems are likely to require certain <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">adjustments to connect with an MPMC, since the MPMC interface is limited to a single-clock and <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">single-data-width domain. In this paper, we propose efficient techniques to improve the flexibility, <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">latency, and bandwidth of an MPMC. Firstly, MPMC interfaces employ a pair of dual-clock dualport FIFOs at each port, so any multi-clock multi-data-width application system can connect to an <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">MPMC without requiring extra resources. Secondly, memory access latency is significantly <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">reduced because parallel FIFOs temporarily keep the data transfer between the application system <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">and memory. Lastly, a proposed arbitration scheme, namely window-based first-come-first-serve, <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">considerably enhances the bandwidth utilization. Depending on the applications, MPMC can be <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">properly configured by updating several internal configuration registers. The experimental results <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">in an Altera Cyclone V FPGA prove that MPMC is fully operational at 150 MHz and supports up <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">to 32 concurrent connections at various clocks and data widths. More significantly, achieved <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">bandwidth utilization is approximately 93.2% of the theoretical bandwidth, and the access latency <span style="font-size: 11pt; color: #000000; font-style: normal; font-variant: normal;">is minimized as compared to previous designs.</span></span></span></span></span></span></span></span></span></span></span></span></span></span></span><br class="Apple-interchange-newline" /></span>}, number={3}, journal={Vietnam Journal of Science and Technology}, author={NGUYEN, Xuan-Thuan and LE, Duc-Hung and BUI, Trong-Tu and HUYNH, Huu-Thuan and PHAM, Cong-Kha}, year={2018}, month={Jun.}, pages={357–369} }