Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications

Nguyen Dang Chien, Luu The Vinh
Author affiliations

Authors

  • Nguyen Dang Chien Department of Electrical Engineering, National Chi Nan University, Nantou 54561, Taiwan
  • Luu The Vinh Faculty of Electronic Technology, Industrial University of Ho Chi Minh City, Ho Chi Minh City 727905, Viet Nam

DOI:

https://doi.org/10.15625/2525-2518/51/6/11642

Abstract

This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fraction should be designed approximately 0.8 because using lower Ge fractions causes severe short-channel effects while with higher values does not significantly improve the device performance but may create big difficulties in fabrication. Based on simultaneously optimizing the subthreshold swing, on- and off-currents, optimum values of source doping, drain doping and length of the proposed device are approximately 1020 cm-3,                1018 cm-3, and 10 nm, respectively. The 8 nm graded Si/SiGe TFET with optimized device parameters demonstrates high on-current of 360 μA/μm, low off-current of 0.5 pA/μm, low threshold voltage of 85 mV and very steep subthreshold swing of sub-10 mV/decade. The designed TFET with graded Si/SiGe heterojunction exhibits an excellent performance and makes it an attractive candidate for future LSTP technologies because of its reality to be fabricated with existing FET and SiGe growth techniques.


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Published

06-03-2018

How to Cite

[1]
N. D. Chien and Luu The Vinh, “Design optimization of extremely short-channel graded Si/SiGe heterojunction tunnel field-effect transistors for low power applications”, Vietnam J. Sci. Technol., vol. 51, no. 6, pp. 757–768, Mar. 2018.

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Articles