A flexible high-bandwidth low-latency multi-port memory controller

Xuan-Thuan NGUYEN, Duc-Hung LE, Trong-Tu BUI, Huu-Thuan HUYNH, Cong-Kha PHAM
Author affiliations

Authors

  • Xuan-Thuan NGUYEN The University of Electro-Communications, 1-5-1 Chofugaoka, Chofu, 182-8585Tokyo, Japan
  • Duc-Hung LE University of Science, Vietnam National University –Ho Chi Minh City, 227 Nguyen Van Cu, District 5, Ho Chi Minh City, Viet Nam
  • Trong-Tu BUI University of Science, Vietnam National University –Ho Chi Minh City, 227 Nguyen Van Cu, District 5, Ho Chi Minh City, Viet Nam
  • Huu-Thuan HUYNH University of Science, Vietnam National University –Ho Chi Minh City, 227 Nguyen Van Cu, District 5, Ho Chi Minh City, Viet Nam
  • Cong-Kha PHAM The University of Electro-Communications, 1-5-1 Chofugaoka, Chofu, 182-8585Tokyo, Japan

DOI:

https://doi.org/10.15625/2525-2518/56/3/11103

Abstract

Multi-port memory controllers (MPMCs) have become increasingly important in many modern applications due to the tremendous growth in bandwidth requirement. Many approaches so far have focused on improving either the memory access latency or the bandwidth utilization for specific applications. Moreover, the application systems are likely to require certain adjustments to connect with an MPMC, since the MPMC interface is limited to a single-clock and single-data-width domain. In this paper, we propose efficient techniques to improve the flexibility, latency, and bandwidth of an MPMC. Firstly, MPMC interfaces employ a pair of dual-clock dualport FIFOs at each port, so any multi-clock multi-data-width application system can connect to an MPMC without requiring extra resources. Secondly, memory access latency is significantly reduced because parallel FIFOs temporarily keep the data transfer between the application system and memory. Lastly, a proposed arbitration scheme, namely window-based first-come-first-serve, considerably enhances the bandwidth utilization. Depending on the applications, MPMC can be properly configured by updating several internal configuration registers. The experimental results in an Altera Cyclone V FPGA prove that MPMC is fully operational at 150 MHz and supports up to 32 concurrent connections at various clocks and data widths. More significantly, achieved bandwidth utilization is approximately 93.2% of the theoretical bandwidth, and the access latency is minimized as compared to previous designs.

Downloads

Download data is not yet available.

Downloads

Published

11-06-2018

How to Cite

[1]
X.-T. NGUYEN, D.-H. LE, T.-T. BUI, H.-T. HUYNH, and C.-K. PHAM, “A flexible high-bandwidth low-latency multi-port memory controller”, Vietnam J. Sci. Technol., vol. 56, no. 3, pp. 357–369, Jun. 2018.

Issue

Section

Electronics - Telecommunication